JTAG and Boundary Scanning

Similar to In-Circuit Test (ICT), JTAG / Boundary Scan utilizes thousands of test points – with only four test access points. Therefore, expensive bed of nail fixtures is redundant The following image shows the architecture of a typical Boundary
Scan IC. The Boundary Scan cells are integrated between core logic and physical contact pins. They enable the test of connections between the pins of IC's, even those without Boundary Scan cells.

JTAG / Boundary Scan is very versatile and can be utilized in the
entire production process, e.g. for emulation, design verification,
prototype and production test as well as on-chip and in-system programming.

Global Electronics Testing Services offers wide range of components testing from basic DC limited function to full DC/AC function test at temperature including up-screening of all type of devices.   As a solution provider our engineering team is ready help.

Extended Boundary Scan Test Flash / PLD / MCU Programming

- Standard tests (infra, intercon, cluster, memory)
- Advanced algorithmic cluster test (Waveform, HLL)
- Test and diagnosis through simulation (IEEE 1445)
- Built-in self-test (BIST) for chips / boards / systems
Analog network test (IEE49.4)
- Advanced algorithmic mixed signal test (scripts)
- Interactive tests for sensors and actors
- Control of FPGA based test instruments

-  Boundary Scan high-­speed Flash programming
-  Emulation based Flash programming
-  On-chip Flash programming of MCU's
-  Serial Flash programming by external access
-  PLD programming (JAM / STAPL / SVF)
-  Parallel PLD programming (IEEE 1532)

Control of External Instruments Graphical Analyzing and Debugging

-  Interactive test with In-­Circuit Tester pins
-  Interactive test with Flying Probes
-  Interactive test with Functional Test I/O
-  Interactive control of software interfaces

-  BSDL verification via graphical device library
-  Adaptive analysis of fault coverage in layout
-  Cross debugging in schematic and layout
-  Test program debugging with hardware monitoring
-  Hardware analysis per interactive layout Pin Toggle

Dynamic Emulation Test (ET)  

-  For memories (sRAM, dRam)
-  For bus devices
-  For system interfaces