JTAG and Boundary Scan

JTAG and Boundary Scanning

Similar to In-Circuit Test (ICT), JTAG / Boundary Scan utilizes thousands of test points – with only four test access points. Therefore, expensive bed of nail fixtures is redundant The following image shows the architecture of a typical Boundary
Scan IC. The Boundary Scan cells are integrated between core logic and physical contact pins. They enable the test of connections between the pins of IC’s, even those without Boundary Scan cells.

JTAG / Boundary Scan is very versatile and can be utilized in the entire production process, e.g. for emulation, design verification,
prototype and production test as well as on-chip and in-system programming.

Global Electronics Testing Services offers wide range of components testing from basic DC limited function to full DC/AC function test at temperature including up-screening of all types of devices. As a solution provider our engineering team is ready to help.

Extended Boundary Scan Test
– Standard tests (infra, intercon, cluster, memory)
– Advanced algorithmic cluster test (Waveform, HLL)
– Test and diagnosis through simulation (IEEE 1445)
– Built-in self-test (BIST) for chips / boards / systems
Analog network test (IEE49.4)
– Advanced algorithmic mixed signal test (scripts)
– Interactive tests for sensors and actors
– Control of FPGA based test instruments

Flash / PLD / MCU Programming
– Boundary Scan high-­speed Flash programming
– Emulation based Flash programming
– On-chip Flash programming of MCU’s
– Serial Flash programming by external access
– PLD programming (JAM / STAPL / SVF)
– Parallel PLD programming (IEEE 1532)

Control of External Instruments
– Interactive test with In-­Circuit Tester pins
– Interactive test with Flying Probes
– Interactive test with Functional Test I/O
– Interactive control of software interfaces

Graphical Analyzing and Debugging
– BSDL verification via graphical device library
– Adaptive analysis of fault coverage in layout
– Cross debugging in schematic and layout
– Test program debugging with hardware monitoring
– Hardware analysis per interactive layout Pin Toggle

Dynamic Emulation Test (ET)
– For memories (sRAM, dRam)
– For bus devices
– For system interfaces

What is a JTAG/boundary scan?

JTAG boundary scan technology provides access to many logic signals of a complex integrated circuit, including the device pins. The signals are represented in the boundary scan register (BSR) accessible via the TAP. This permit testing as well as controlling the states of the signals for testing and debugging. Therefore, both software and hardware (manufacturing) faults may be located, and an operating device may be monitored.

The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan register cell) adjacent to each component pin so that signals at component boundaries can be controlled and observed using scan testing principles.

The boundary-scan register cells for the pins of a component are interconnected to form a shift-register chain around the border of the design, and this path is provided with serial input and output connections and appropriate clock and control signals. Within a product assembled from several integrated circuits, the boundary-scan registers for the individual components could be connected in series to form a single path through the complete design, as illustrated in Figure 1

For component level testing, we use the boundary-scan register to access each pin for the purpose of driving stimuli, capturing responses or both in the case of bi-directional pins. Also, if the optional IDCODE instruction and associated identification register is implemented, the IC manufacturers code, the part number and its revision will be checked. It is required that this infrastructure be operational before any other test to yield valid results.


Figure 1 —Boundary-scannable board design allowing 4 ICs to be tested together using the JTAG/Boundary Scan Method

Figure 2 —Boundary-scan for component level testing to drive each device pin and verify manufacturer ID code.

Currently, we offer PXI-digital pattern recognition without a BSDL§ file which are necessary for the application of boundary-scan for board and system level testing and in-system programming. BSDL files contain a full description of the Boundary-scan functionality within a chip.

With PXI-digital pattern evaluation without a BSDL file we perform ID code check, AC/DC test, and EXTEST, by using a tap controller.



Figure 3 —Verification of device manufacturer’s ID code with PXI-digital pattern readout. .

With the BSDL file we can easily get all of the instruction code and definition for each pin. We do not need to possess any information except the pinout of the TAP controller. Our system can verify all the I/O pins and toggle between them in one attempt. The I/O pins can be configured to either the high and low state or oscillating mode. Once the I/O is configured, we can make sure that all the I/O pins can source the desired current or not in open and short status. Also , the system is already integrated into our labview based ATE, which is owned and developed by Global ETS. Once tested with the ATE system , the lead time can be shortened by a few days and all the AC/DC data will be read and recorded by our servers.


The Modern FPGA/MCU has thousands of pins on one chip. This renders traditional testing methods very expensive and time-consuming for evaluating even a single chip. The boundary-scan method has proven itself as an invaluable tool in testing today’s complex digital devices. Boundary scans enable a fast and inexpensive method to perform testing during environment stress screening with pin-level diagnosis upon failure. The firmware updates without disassembly are required.

Figure 5 —Lab-view based ATE system